The component that powers artificial intelligence looks less and less like a standalone chip. Under the hood, multiple pieces of silicon and stacks of memory work together, linked by microscopic connections. Their layout, power delivery and cooling determine performance as much as transistor size does. Packaging, long treated as the final manufacturing step, is becoming a strategic battleground. To understand what is at stake for September 2026, we need to revisit the changes already documented, then distinguish what they allow us to anticipate from developments that remain uncertain.
Nanometers no longer tell the whole story
For decades, the semiconductor story revolved around a single race: shrinking features to fit more transistors into a given area. This remains an essential driver. But advanced processes are increasingly expensive to develop and operate, while the gains from moving to a new generation depend heavily on the application. Excellent compute logic is not enough if data arrives too slowly.
Packaging encompasses the techniques that protect circuits and provide their electrical and mechanical connections to the system. In its advanced form, it no longer merely encases silicon: it organizes multiple components into a coherent whole. The right question is therefore no longer just “how many transistors?” but also “over what distance do they communicate, with what bandwidth and power consumption?”
Chiplets: divide to manufacture better
A chiplet is a small, specialized chip designed to work with others in the same package. Rather than manufacturing a huge monolithic circuit, a company can separate compute cores, input/output circuitry or certain acceleration functions. AMD has done much to popularize this approach in its Ryzen and EPYC processors. Intel has also adopted it, notably with the different tiles in Meteor Lake.
The benefits are as much about manufacturing as architecture. A defect can render a large circuit unusable; splitting certain functions into smaller elements can improve manufacturing yields. It also allows the most expensive processes to be reserved for blocks that genuinely benefit from them. Interfaces or certain analog circuits can remain on more mature technology. The same building block can also be reused across several products.
But this partitioning comes at a cost. Interconnects, substrates, assembly operations and testing all have to be paid for. Communication between chiplets consumes energy and introduces latency. Depending on the design and production volumes, a monolithic chip can still make sense. Chiplets involve trade-offs; they are not a universal recipe for cutting costs.
A standard does not yet make a construction kit
Introduced in 2022, the UCIe standard aims to facilitate communication between chips within the same package. Its promise is to make certain interfaces less proprietary and foster an ecosystem. However, assembling chiplets from different suppliers requires more than a shared electrical language. Dimensions, power delivery, heat dissipation, design tools and validation procedures must all be coordinated. A catalog of interchangeable building blocks remains a prospect, not a widespread reality.
HBM brings memory closer to compute
In artificial intelligence, memory has become a cornerstone. Accelerators must continually move vast amounts of parameters and data. HBM, short for High Bandwidth Memory, stacks multiple layers of DRAM, linked in particular by connections that pass through the silicon. These stacks sit close to the processor and communicate with it through very wide interfaces.
A useful analogy is a factory: adding more machines achieves little if raw materials arrive along a narrow road. HBM widens that road and shortens the journey. It can reduce the energy consumed per bit transferred compared with more distant memory solutions, without necessarily making the overall system energy-efficient. Accelerators such as Nvidia’s H100 and AMD’s Instinct MI300 have already demonstrated how much this proximity shapes the architecture.
This sophisticated memory depends on a demanding industrial supply chain involving companies including SK hynix, Samsung and Micron. Available capacity is not simply a matter of how many memory chips are manufactured: stacking, testing and qualification also count. As early as 2023 and 2024, the AI boom put pressure on various stages of this chain. Looking ahead to September 2026, caution remains warranted: increasing logic production alone does not guarantee that more accelerators can be shipped.
From 2.5D to 3D: closer together without overheating
Two main approaches underpin this integration. In 2.5D, multiple components are placed side by side on an interconnection substrate, often called an interposer. In 3D, circuits are stacked and connected vertically. TSMC’s CoWoS platform is a prime example of the integration used with HBM; Intel’s developments include EMIB and Foveros. These technologies address different needs and are not simply interchangeable.
Stacking shortens some connections and can improve density or communication efficiency. But heat still has to escape. Placing a highly active circuit beneath another makes heat removal more difficult. Power delivery also becomes challenging, as do mechanical stresses between materials. Final performance therefore depends on very concrete choices: block placement, thermal interfaces, allowable power and server cooling.
The challenge extends to quality control. Each element must be tested as thoroughly as possible before assembly, and the complete system must then be validated. If an operation fails late in the process, it can hold up or compromise several expensive components. Advances in hybrid bonding, which enable very fine connections, must therefore be accompanied by industrial-scale control of surfaces, alignment and defects.
The new battle for manufacturing capacity
This shift is reshaping roles. Foundries such as TSMC and assembly and testing specialists, notably ASE and Amkor, operate at different levels of the supply chain. Memory manufacturers are becoming even more critical. The boundary between chip design and package design is blurring: decisions must be made jointly, long before production.
For governments, funding a chip fabrication plant is therefore not enough. A credible strategy must also consider substrates, assembly equipment, metrology and skills. In the United States, the national program dedicated to advanced packaging, launched under the CHIPS Act, illustrates this growing awareness. In Europe too, resilience requires looking at the entire supply chain rather than a single process-node figure.
What next? Looking ahead to September 2026, the most plausible scenario is not the end of the nanometer race, but its expansion into a two-track contest. Manufacturers must advance both transistor technology and integration simultaneously. The winners could be those that consistently deliver reliable, coolable and economically viable systems, rather than those that merely announce the densest chip. Packaging does not replace process technology: increasingly, it determines what can actually be gained from it.
