A chip measuring just a few millimeters, hidden inside a sensor, can signal a major industrial battle. With RISC-V, designing a processor no longer necessarily means negotiating access to a proprietary architecture. That promise attracts startups, manufacturers and governments concerned about their autonomy. But the leap in scale from a small controller to the brain of a server is enormous. Looking ahead to September 2026, the question is not simply how to make more RISC-V chips: it is how to turn this technical freedom into lasting competition. Here are the documented achievements and the prospects they open up, without treating those prospects as accomplished facts.
An open grammar, not a free factory
RISC-V originated in 2010 at the University of California, Berkeley. It defines an instruction set: the basic operations that software can ask a processor to perform. Adding numbers, moving data, executing a conditional branch: this grammar forms the interface between code and machine. Its specification is open, and using it requires no licensing royalties on the instruction set itself.
The difference from the dominant models is significant. Arm sells licenses for cores and architectures, among other offerings; the x86 world remains centered on Intel and AMD. RISC-V allows other players to design compatible implementations without obtaining comparable commercial permission to use that interface. However, the openness applies to the language, not automatically to the processor’s blueprints. A RISC-V core can remain entirely proprietary.
That distinction makes all the difference to the sector’s economics. Companies such as SiFive and Andes sell RISC-V technologies and support services. Others develop their own cores. In every case, engineers, design tools, verification and then manufacturing must be paid for. An openly accessible architecture lowers one barrier; it does not make a chip free.
Why small processors are leading the way
Microcontrollers offer fertile ground. In a connected device, industrial equipment or an electronic accessory, the processor often runs a limited program controlled by the manufacturer. It does not have to run decades’ worth of consumer applications. Adapting software to a new architecture therefore becomes a clearly bounded project rather than a bet on an entire ecosystem.
Espressif illustrates this: several of its ESP32 chips, including the ESP32-C3, use RISC-V. For a developer, the decisive argument is not necessarily philosophical. It comes down to the component’s price, power consumption, connectivity and the quality of the available tools. The open architecture wins when it fades into the background behind a practical product.
RISC-V also appeals to designers of complex systems for internal tasks: controlling a hardware block, managing certain functions or coordinating an accelerator. A chip can therefore incorporate RISC-V cores without its user knowing. This quiet spread matters: it builds expertise and reusable libraries. But it does not, by itself, prove that the architecture is ready to replace a computer’s main processor.
Performance must be built, not proclaimed
The leap toward high-performance processors has nevertheless begun. SiFive has introduced cores aimed at more demanding uses; players such as Ventana are developing technologies geared toward data centers. In Europe, the EPI initiative has also explored RISC-V for computing accelerators. These projects demonstrate genuine ambition, without proving broad parity with the best competing offerings.
The instruction set is only one ingredient. Performance depends on the microarchitecture: the ability to execute several operations simultaneously, branch prediction, cache organization and memory access. It also depends on the manufacturing process and system integration. Two RISC-V processors can have as little in common in terms of performance as two vehicles that use the same fuel.
Vector extensions, in particular, enable efficient processing of data sequences. They are useful for scientific computing and certain artificial intelligence workloads. But having suitable instructions is not enough: compilers capable of using them, optimized libraries and an efficient supply of data are also needed. For AI, the specialized accelerator and its software environment often remain more important than the architecture of the control core.
Software is the real test
RISC-V is not starting from scratch. Linux, the GCC and LLVM compilers, and several real-time operating systems already offer support. Linux distributions and communities are working to make the whole stack usable. Yet “the system boots” and “a business can operate this system for years” are two very different milestones.
On a server, monitoring tools, virtualization, database engines and application dependencies must be checked. On a personal computer, graphics drivers, power management, browsers and software distributed only in binary form add to the list. Every gap can turn hardware savings into additional integration costs. Established architectures enjoy a considerable cumulative advantage here.
Avoiding an incompatible patchwork
RISC-V’s modularity is both its strength and its risk. A manufacturer can choose standard extensions and add custom features. This flexibility suits a specialized product; it complicates the distribution of the same software across very different machines. Standardized profiles are intended precisely to define coherent sets of features. Their adoption and rigorous compliance testing will be essential to limit fragmentation.
Autonomy still faces industrial constraints
Geopolitics explains some of the interest. An open architecture reduces dependence on a licensing provider and makes it easier to access a shared specification. It is attracting particular interest in China and Europe. RISC-V International, the organization overseeing standardization, is based in Switzerland. But that governance does not shield the entire industrial supply chain from trade tensions.
Electronic design tools, certain intellectual property blocks, advanced foundries and packaging remain areas of concentrated supply. A company can control its RISC-V core while depending on foreign suppliers to produce its chip. Export restrictions may affect these technologies or certain technical exchanges. RISC-V is a tool for greater autonomy, not a turnkey solution for sovereignty.
To genuinely broaden competition, the ecosystem will therefore have to move beyond demonstrators: it must offer components that are available, documented, properly secured and maintained. In the automotive and industrial sectors, qualification and long-term supply availability matter as much as performance. New entrants may also become specialist suppliers rather than direct rivals to established giants.
What next? The most credible scenario for September 2026 is progress in targeted markets rather than a sudden replacement of Arm or x86. The indicators to watch are tangible: software usable without extensive adaptation, repeat orders, chip availability and support commitments. RISC-V will have changed competition when more buyers can choose an alternative solution without having to become processor integrators themselves.
